The invention relates generally to fabrication of wafer assemblies, and more particularly to fabrication of arrays of transducers and/or sensors, such as those used in ultrasonic systems.
Ultrasonic systems, such as systems utilizing capacitor micromachined ultrasonic transducers (cMUTs), have been used in multiple applications ranging from non-destructive evaluations to medical diagnostics and therapy. CMUT based systems may integrate multiple units, such as microelectromechanical system (MEMS) devices and complementary metal oxide semiconductor (CMOS) chips/dies, where such devices work in conjunction with one another. The MEMS devices employed in such systems are, typically, fabricated in multiple arrays on a wafer. Accordingly, the CMOS devices may be used to control the operation of the transducers and/or sensors. The CMOS dies are, typically, fabricated using standard fabrication methods, which may include very large scale integration (VLSI) or ultra large scale integration (ULSI) fabrication methods. Accordingly, fabrication of the CMOS dies is performed on wafers that are separate from those on which the MEMS devices are fabricated.
Current fabrication methods for integrating MEMS and CMOS devices are relatively expensive and provide a relatively low yield. Further, current fabrication methods fail to integrate MEMS and CMOS arrays at fine pitches using current industry standards. Conventionally, either an interposer having through wafer vias, and/or electrical bump bonds are employed for integrating MEMS and CMOS devices. However, both of these techniques are relatively expensive for systems with high channel count. Also, as the input/output (I/O) pitch decreases below 180 microns, it becomes even more challenging to interconnect both the wafers using a conventional flip chip attach method, especially when one or more of the wafers are thinned. Occasionally, MEMs arrays are directly fabricated on top of a silicon CMOS wafer, but this technique suffers from a number of issues including combined CMOS/MEMs yield.
Therefore there is a need to explore new methods and devices to integrate MEMS arrays with an array of CMOS devices, both fabricated on separate substrates.